The present invention relates to a semiconductor memory device, and more particularly to a test mode control circuit controlling the test of an internal circuit.
In general, in the development and production of semiconductor memory device products, a test mode is used for detecting the characteristics and functions of the products required for the specification thereof, and confirming whether the functions required in mounting the components thereof are normally performed in a correct manner.
Referring to FIG. 1, a conventional test control circuit controlling the test mode receives test mode signals TM_IN1-TM_INn corresponding to the number of test mode items, latches the input test mode signals TM_IN1-TM—INn in response to a plurality of latches 100, amplifies the latched signals in response to a plurality of drivers 120, respectively, and outputs the amplified signals in the plurality of drivers 120 to the plurality of test mode flag signals TM_FLAG1˜TM_FLAGn.
And, the plurality of test mode flag signals TM_FLAG1˜TM_FLAGn are input to a plurality of test mode enable signal generators 140, respectively, through the global lines GL. The input plurality of test mode flag signals TM_FLAG1˜TM_FLAGn are combined with addresses ADDR <0:7> designating a test mode item code in the plurality of test mode enable signal generators 140 to be output to a plurality of test mode enable signals TM_EN1˜TM_ENn.
As described above, the conventional test control circuit combines the test mode signals TM_IN1˜TM_1Nn with the addresses ADDR<0:7>, respectively, to generate a plurality of test mode enable signals TM_EN1˜TM_ENn controlling various kind of enables. To this end, the conventional test control circuit comprises latches, drivers, and global lines GL, as many as, the test mode items.
Therefore, the conventional semiconductor memory devices suffer a problem that many areas are required for arranging circuits and lines relating to test modes.